1. Field of the Invention
This invention relates generally to digitally controlled oscillators and more particularly to a compact, high power supply rejection ratio (PSRR), low power semiconductor digitally controlled oscillator (DCO) architecture.
2. Description of the Prior Art
Deep sub-micron CMOS technology demands that most analog circuits be implemented in the digital domain; while high supply noise associated with digital circuitry demands a high Power Supply Rejection Ratio (PSRR) for the circuit. Digitally controlled oscillators are popular building blocks in phase lock loop (PLL) circuits that employ deep sub-micron CMOS technology where more and more analog circuits are implemented in the digital domain. A simple, robust, high power supply rejection (PSR) DCO is a must for system integration due to high supply noise associated with digital circuitry.
A digital controlled oscillator (DCO) can be implemented in many ways. Typically, a digital-to-analog converter (DAC) is used to convert a digital code into an appropriate voltage or current which directly controls the oscillation frequency. Other implementations digitally control the effective R, C and/or L of the associated ring oscillators.
FIGS. 1-4 shows 4 popular DCO architectures. The DCO 100 depicted in FIG. 1 changes the oscillation frequency by digitally controlling the resistance 102. The DCO 200 depicted in FIG. 2 changes the oscillation frequency by digitally controlling the capacitance 202. The DCO 300 depicted in FIG. 3 changes the oscillation frequency by changing the control voltage through DAC 302, then applying this voltage to a typical voltage controlled oscillator (VCO) 304. The DCO 400 depicted in FIG. 4 changes the oscillation frequency by changing the control current through DAC 402, then mirroring the current to a current controlled oscillator (ICO) 404.
The DCO architectures 100, 200 shown in FIGS. 1 and 2 are problematic in that for a given required frequency step resolution, the same switches and R/C structures need to be implemented on every oscillator stage. This not only increases the area, but also introduces unnecessary noise on the oscillator due to the switch activities near by. The DCO architecture 300 shown in FIG. 3 is problematic in that voltage is more sensitive to noise; and the oscillator still needs some xe2x80x9cbufferxe2x80x9d on top to have good PSRR. The DCO architecture 400 shown in FIG. 4 is problematic in that more power is wasted in the DAC 402 and current mirror 406, and the possible mismatch in the mirroring current.
It is therefore advantageous and desirable in view of the foregoing, to provide a high PSRR, low power semiconductor digitally controlled oscillator (DCO) architecture that employs only one simple current steering D/A converter directly on top of multi-stage current controlled oscillators.
The present invention is directed to a high PSRR, low power semiconductor digitally controlled oscillator (DCO) architecture that employs only one simple current steering D/A converter directly on top of a multi-stage current controlled oscillator. The architecture provides a good building block for many circuit applications, e.g., all digital phase lock loops, direct modulation transmitters for wireless devices, and the like.
According to one embodiment, a digitally controlled oscillator (DCO) comprises a current controlled oscillator; a current source configured to provide a bias current for the current controlled oscillator; and no more than one current steering digital-to-analog converter (DAC) directly on top of the current controlled oscillator; wherein the DAC is configured to selectively steer a tuning current provided by the DAC into the current controlled oscillator to control the frequency of oscillation provided by the current controlled oscillator.
According to another embodiment, a digitally controlled oscillator (DCO) comprises a multi-stage current controlled oscillator; a current source directly on top of the current controlled oscillator and configured to provide a bias current for the current controlled oscillator; and at least one current steering digital-to-analog converter (DAC) directly on top of the current controlled oscillator and configured to generate and steer a tuning current into the current controlled oscillator to control its frequency of oscillation.
According to yet another embodiment, a method of controlling an oscillation frequency comprises the steps of providing a high PSRR, low power semiconductor digitally controlled oscillator (DCO) that employs only one simple current steering D/A converter directly on top of a multi-stage current controlled oscillator; and generating and steering a current into the multi-stage current controlled oscillator via the D/A converter to control the frequency of oscillation.